Mobile radio systems today use various mobile radio standards such as the Global System for Mobile communication (GSM), Enhanced Data Rates for GSM Evolution (EDGE), Universal Mobile Telecommunications Standard (UMTS), or others. In this case, radio-frequency signals are used for transmission. Other systems also use radio-frequency signals for data transmission.
To generate and receive the radio-frequency transmission/reception signals, use is increasingly being made of digitally controlled oscillators, DCOs. As its output signal, a DCO generates a radio-frequency signal on the basis of a digital frequency word. In addition, a digital phase locked loop with a DCO on a semiconductor body requires less space than a corresponding phase locked loop with an analogue-controlled voltage controlled oscillator, VCO. A digitally implemented phase locked loop for frequency synthesis or signal modulation can also be transferred to a next semiconductor process generation more easily.
A digital phase locked loop usually comprises a digitally controlled oscillator for generating an oscillator signal. The oscillator signal is fed back to a comparator directly or via a frequency divider, which may have an adjustable divider ratio. In this case, the comparator usually has a second input for supplying a reference frequency signal. The output of the comparator outputs a digital error word which is usually supplied to a control input of the digitally controlled oscillator via a digital loop filter.
The comparator may be in the form of a phase detector, in the form of a frequency detector or in the form of a combined phase/frequency detector. In the case of fully digital phase locked loops, phase detection is an element which should not be ignored. The comparator delivers a digital word as a measure of a detected phase for the returned oscillator signal, which is compared with a nominal value, likewise in digital form. A nominal/actual value discrepancy is output to the control loop as a digital error word. It is desirable for the comparator to have a high level of accuracy and to be insensitive to external interference. In addition, a phase recognition area of the comparator needs to be designed such that discrepancies from the nominal signal can be compensated for within a predetermined framework. Such discrepancies can be caused by timing inaccuracies, such as timing jitter, in the reference frequency signal or by analogue phase noise on account of analogue components in the oscillator, for example.
By way of example, the comparator may be implemented as a frequency detector which is designed using a fully synchronous counter with a subsequent differentiator. However, a fully synchronous counter of this kind can be difficult to implement, particularly when the oscillator signal has high input frequencies. By way of example, a desired level of synchronism makes great demands on delayed properties of the components used. In addition, a frequency detector of this kind requires a high power consumption.
The use of a differentiator downstream of the counter in the frequency detector also prompts conversion of the phase information into frequency information, which should be converted back into phase information again in the loop filter using an integrator. This results in an increase in the complexity in the digital phase locked loop.
In another possible embodiment, the comparator comprises a counter, which is used as a phase detector for coarse quantization of the phase information in the oscillator signal, and a time/digital converter (time-to-digital converter), TDC. In this case, the TDC can be used for finer phase quantization. However, the additional TDC increases the complexity of the comparator or the phase locked loop in this case too.